Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
In multi-core processor architectures, multiple processor cores may be included in a single integrated circuit die or on multiple integrated circuit dies that are arranged in a single chip package. A cache may be used to store data for access by one or more of the processor cores. The data can be a subset of data stored in a larger memory that is typically located outside of the die/chip. Each processor may be provided with a private cache that stores data for the processor. There may also exist other caches that are shared by multiple processors. As a single piece of data may be stored in multiple private and shared caches, a cache coherence protocol may be configured to keep track of the data stored in multiple caches. The cache coherence protocol may be configured to help ensure that multiple requests for data consistently result in the appropriate latest versions of the same data being returned. One or more programs, which may utilize or generate at least some of the data, may be executed on one or more of the cores.